Study of 3-D Line Edge Roughness (LER) in Vertical Channel Array Transistor for DRAM

Line edge roughness (LER) is an undesirable phenomenon that arises during semiconductor fabrication processes, causing fluctuations in the characteristics of semiconductor devices and potentially leading to significant yield degradation. Consequently, LER must be meticulously considered before fabricating integrated circuits. In this study, we present an approach for implementing and analyzing LER in vertical channel array transistors (VCATs) with a gate-all-around (GAA) structure for dynamic random access memory applications. Initially, we propose a method for reliably implementing LER in GAA semiconductor devices. Next, we extend the method to more complex structures beyond the basic cylindrical GAA structure. Utilizing the proposed method, we investigate the impact of LER on various VCAT device configurations by examining DC performance metrics such as IOFF, IDS,LIN, IDS,SAT, VT,LIN, VT,SAT, IOV,LIN, and IOV,SAT. Additionally, we explore AC performance metrics (THOLD, TREAD, and TWRITE) through mixed-mode simulations. The results show that the parameters influencing LER-induced fluctuations in VCATs vary depending on the transistor’s operating region (i.e., whether the transistor is turned on or not).