Low-Power CRC-BCH Error Correction Integrated with LFSR and Clock Gating: A Comparative Analysis

This paper presents a low-power, Clock-Gated Integrated CRC-BCH (Cyclic Redundancy Check - Bose-Chaudhuri-Hocquenghem) Error Correction Code (ECC) architecture designed to address single-event upsets (SEUs) and multi-cell upsets (MCUs) in space applications. ECCs are essential for ensuring reliable data transmission and reception in avionics and memory systems, which are increasingly prone to faults due to cosmic radiation, thereby necessitating robust fault detection and correction mechanisms. In this work, a Linear Feedback Shift Register (LFSR) based fault injector simulator was introduced within the CRC-BCH module to evaluate its error detection and correction capabilities under various fault scenarios. Additionally, a Clock Gating Integrated Circuit (CGIC) was implemented to optimize power consumption. The proposed design achieves significant power efficiency while maintaining high performance and reliability, making it highly suitable for power-sensitive, high-reliability environments.