A Fast SerDes Equalizer Effect-Included Worst Eye Diagram Estimation Method for High-Speed Serial Links

In this paper, a fast SerDes equalizer effect-included worst eye diagram estimation method is proposed for high-speed serial links. The proposed approach analytically integrates the effects of linear and nonlinear equalizers in the frequency and time domains, respectively, based on the behavior of the equalizers. This approach enables fast single-bit response (SBR) calculations without requiring input/output buffer information specifications, i.e., an algorithmic model interface (IBIS-AMI) model-based transient simulation. Additionally, a modified peak distortion analysis (PDA)-based worst eye estimation method was employed, including the outer contours. To validate the proposed method, tests were conducted in a peripheral component interconnect express (PCIe) Gen 6.0 channel environment configured with various equalizer combinations and different loss conditions. The proposed method achieves eye contour results comparable to those in conventional circuit simulations, operating up to 255 times faster than bit-by-bit methods and up to 66 times faster than statistical methods. The proposed method offers significant advantages in environments that require rapid exploration of optimal channel and equalizer combinations, providing substantial time savings and efficient evaluations.