LUT Level Information Flow Tracking for FPGA Design Security Verification

As the core engine of modern communication systems, digital circuits are encountering significant security risks of cyber-attacks. Hardware information flow tracking (IFT) is a powerful tool for integrated circuit design security verification and vulnerability detection. While there are a large body of hardware IFT methods at different levels of abstraction, look-up-table (LUT) level IFT is still an open research challenge due to the huge number of possible LUT configurations that all correspond to varying IFT behaviors. In this work, we make the first move towards LUT level IFT for field programmable gate array (FPGA) design security verification. Specifically, we design an algorithm that enables automatic creation of the precise IFT model for an arbitrary LUT and the generation of fine-grained IFT logic for FPGA netlists. Through using the generated IFT logic as the security model, we can formally prove security properties and hunt for security vulnerabilities. Experimental results have demonstrated that our method can detect the timing channels and hardware Trojans residing in the synthesized FPGA netlists of Trust-Hub benchmarks. Our work complements the spectrum of hardware security verification solutions at both the FPGA netlist and bitstream ends, which fills in the gap of post-synthesis FPGA design security verification tools.