Low-Power and Superior Performance Design of Ternary Logic Cells Using CNFET and MOSFET Devices for VLSI Applications

This work explores the implementation of ternary logic using novel devices, particularly Carbon Nanotube Field Effect Transistors (CNFETs). CNFETs leverage single-walled carbon nanotubes as conducting channels, and by adjusting the diameter of the carbon nanotubes, we can control the device's threshold voltage. This characteristic makes CNFETs well-suited for ternary logic, as we can easily create Low Voltage Threshold (LVT) and High Voltage Threshold (HVT) devices required for implementing ternary logic. Optimized MOSFET and CNFET, N, and P-channel devices are benchmarked and compared at 45 nm technology node. Furthermore, we present the design and functionality of ternary inverters using both MOSFETs and CNFETs, including Negative Ternary Inverter (NTI), Positive Ternary Inverter (PTI), and Standard Ternary Inverter (STI). The performance of all the logic cells mentioned in the paper was benchmarked and it is observed that CNFET ternary cells have lower PDP compared to MOSFET ternary cells. A decrease of 23.78% and 20.78% in PDP is observed for NTI and PTI logic cells, respectively, and a decrease of 29.65% and 29.35% is observed for STI 1 and STI 2 logic cells, respectively.