Leveraging Dual Output LUTs with Pipelining for Efficient BCD to Binary Converter on FPGA

Decimal operands expressed in BCD is often the convenient data format used in embedded systems and human-centric applications. For optimized arithmetic computation on hardware where binary arithmetic can be conveniently processed, input BCD operands should first be converted to binary. This paper explores the versatility of FPGA specific logic primitives, namely the dual output Look-Up Tables (LUTs) and carry chain for efficient realization of parallel and pipelined architectures to optimize throughput and resource utilization for BCD to binary conversion architectures. Primitive instantiation was adopted to ensure design optimization, which involved direct configuration of FPGA logic primitives. The utility ratio of the configured FPGA primitives was increased to extract the best performance. Experimental results demonstrate a good trade-off in speed and area for our proposed architectures when compared with existing designs. We have investigated multiple implementation variants for the addition tree, which serves as a crucial functional logic block in the converter design.