Meta-Heuristic Optimization of Custom Heterogeneous Blocks Defined eFPGA Design

Modern Field-Programmable Gate Arrays (FPGAs) are highly versatile, with reconfigurable logic functionality that allows designers to create custom designs. Unlike traditional fixed-function integrated circuits, FPGAs are reconfigured multiple times to perform different tasks, making them ideal for various applications. An Embedded FPGA (eFPGA) takes the concept of an FPGA and integrates it as an IP core within a larger System-on-Chip (SoC) or Application-Specific Integrated Circuit (ASIC). The proposed work employs Non-dominated Sorting Genetic Algorithm-II (NSGA-II) to evolve efficient and high-performing eFPGA architectures with reduced critical path delay and power defined by a sufficient number of Configurable Logic Blocks (CLBs), custom Digital Signal Processors (DSPs) and Block RAM (BRAMs) for targetting workload under consideration. As a result, this work presents a well-balanced eFPGA architecture layout obtained for four workloads equipped with different numbers of heterogeneous and configurable logic blocks. The results showed a significant improvement of 44.62% in hardware parameters.