FARAD: Automated Formal Verification of Approximate Restoring Array Dividers

Approximate circuits have shown immense potential in the area of error-resilient applications. These circuits have tailored specifications depending on the resilience of an application towards the introduction of approximation. Formal verification is essential to guarantee the approximate circuit matches its tailored specifications. Hence, formal verification of approximate circuits has gained traction in recent years. However, most prior works focused on relaxed equivalence checking, i.e., only ensuring that the approximate circuits are within a specified error bound of the exact circuit. Recently, it was shown that formal error analysis is insufficient to ensure the approximate circuit matches its tailored functional specifications. However, this work was only limited to adders and multipliers. Hence, in this work, we propose a method called FARAD, that guarantees the approximate restoring array divider matches its functional specification. We use the functional specification of the approximate divider to generate the correctors. These correctors are then inserted in the approximate divider to generate the corrected divider. The corrected divider can then be formally verified by performing equivalence checking against a golden reference exact divider. If the corrected divider is equivalent to the golden reference divider, the approximate divider matches its functional specification. We generated more than half a million approximate dividers and verified them using FARAD.