A 94.3-dB SNDR 184-dB FoMs 4th-Order Noise-Shaping SAR ADC With Dynamic-Amplifier-Assisted Cascaded Integrator

This letter presents a fully dynamic 4th-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with the proposed 4th-order cascaded integrator using dynamic-amplifier-assisted and passive integration. This ADC can achieve sharp NTF with only two dynamic amplifiers and is insensitive to process, voltage, and temperature (PVT) variation. The NS-SAR ADC occupies 0.09 mm2 in a 28-nm CMOS process. With a 1-V supply voltage, it consumes $107.38~\mu $ W at 5 MS/s. The measured signal-to-noise and distortion ratio (SNDR) is 94.3 dB over a 100-kHz bandwidth (BW), resulting in a Schreier figure of merit (FoM) of 184 dB and a Walden FoM of 12.6 fJ/conv.-step.