Design and Implementation of High Speed Self-Biased DTDC for Flash ADC

To maximize speed and power economy, the requirement for high speed low power analogue to digital converters (ADC's) is driving towards the adoption of dynamic double tail comparator. The comparator is one of most power hungry block of analog to digital converter and it also directly affects the ADC's overall performance. It is possible to switch on the comparator just when it is required to limit the power usage of ADC. Because of their power economy and great speed, many high speed and low power ADCs employ regenerative comparators. Therefore, a unique self-biased double tail dynamic comparator (DTDC) is developed to improve latch regeneration performance, hence reducing overall latency and enabling use in more hustle flash ADCs. Using GPDK 45nm technology, the suggested comparator is built and simulated in Cadence® Virtuoso Analogue Design Environment. The circuits are tested using a 1.0 Volt DC supply voltage and a clock frequency of 200MHz.