High-Speed, Area-Efficient Three-Operand Pipelined Adder

In high-speed arithmetic circuits, adder efficiency is crucial for system performance. Common adders like Carry Skip, Han-Carlson, and Kogge Stone aim to optimize delay and area but still struggle to balance speed, area, and power. This paper introduces a new three-operand pipelined adder, replacing conventional parallel prefix logic with a streamlined pipelined method. The design combines an adder and subtractor in one unit, using modular logic to handle both functions. Pipelining allows continuous data processing, increasing throughput and reducing critical path delay. This three-operand pipelined adder achieves significant area and delay improvements over traditional designs. Using fewer logic gates and connections makes the design more compact and improves its performance. Simulations and synthesis validate the proposed design's effectiveness, showing major improvements in speed and area, making it valuable for high-speed, area-limited VLSI applications.