Performance Analysis of Vedic Multiplier using Kogge Stone Adder and Reversible Logic

As DSP applications continue to advance, the demand for faster and more power-efficient multipliers persists. Reversible logic emerges as a promising solution to mitigate power dissipation, theoretically offering zero power consumption. Leveraging the efficiency of Vedic mathematics techniques, particularly the Urdhva Tiryakbhayam algorithm, becomes imperative in addressing speed and power concerns in multiplier implementation. This study focuses on implementing an $8 \times 8$ Vedic multiplier utilizing the Kogge Stone Adder and optimizing for power using reversible logic. The design is simulated and synthesized in Cadence tool 180 nm technology. Performance evaluation of the Vedic multiplier is conducted, assessing its area, speed, and power consumption. The performance of Vedic multiplier implemented with conventional gates is compared with the implementation using reversible gates. The comparison shows considerable improvement in power for multiplier with reversible logic. The synthesis results shows that power reduction by $7.2 \%$ over conventional gate implementation. At the same time, the implementation suffers from area and datapath delay overhead by $16.87 \%$ and $27 \%$ respectively.