FPGA Accelerated High Speed Radix-4 Parallel Multiplier

Multiplication is essential in the field of digital systems like DSP, AI and ML. The VLSI field involves the reduction of minimising area, power consumption, delay and improving efficiency. This paper introduces a FPGA accelerated high-speed radix 4 parallel multiplier which reduces delay. The CSA is modified to have a 4-bit adder, two half adders and a 2-bit RCA. It makes the multiplier more efficient by reducing the cell delay. The parallel addition process used here improves performance. The number of logic elements used does not differ from the existing model thus bringing no change in the structure. The proposed multiplier is implemented using VHDL on Altera Quartus II. This makes it useful for applications such as High Performance computing system (HPC), FPGA based systems, Custom ASIC designs, Quantum computing and 5G or future communication systems.