A 22-nm Delta-Sigma Computing-In-Memory SRAM Macro With Near-Zero-Mean Outputs and LSB-First ADCs for Edge AI Processing

This work proposes a static random access memory (SRAM)-based delta-sigma computing-in-memory ( $\Delta \Sigma $ CIM) processor for edge intelligence applications in 22-nm CMOS technology. This $\Delta \Sigma $ CIM processor effectively mitigates redundant operations associated with unchanged input features and adaptively adjusts computing-in-memory (CIM) outputs to achieve a near-zero-mean (NZM) distribution, thereby benefiting the energy-intensive analog-to-digital converters (ADCs). The proposed $\Delta \Sigma $ CIM macro involves three main innovations at the architecture and circuit levels: first, it replaces absolute inputs with deltas computed from consecutive input values, resulting in a notable 35.8% reduction in energy consumption for the CIM array; second, the delta matrix-vector multiplications (MVMs) implemented by $\Delta \Sigma $ CIM array can self-adaptively shift the analog CIM outputs to be NZM distributed, facilitating streamlined centralized data processing; and third, the introduction of a least significant bit first (LSB-first) ADC, whose number of conversions adjust dynamically based on instantaneous input values, allows for efficient analog output conversion of highly concentrated NZM analog data without compromising full-scale range or precision. Compared with state-of-the-art (SOTA) analog SRAM-based CIM macros, this work achieves superior area-energy efficiency product by $1.25{\times }$ with up to 21.38 TOPS/W and 1.44 TOPS/mm2 at full precision of 8b input, 8b weight, and 24b output, through bit-serial inputs and shifter-and-adder.