Minimal Zero-Sequence Circulating Current Modulation Strategy Based on Equivalent Vector Redundancy for Two Paralleled Inverters

Due to the difference of common-mode voltage (CMV), the zero-sequence circulating current (ZSCC) becomes a major issue in two paralleled voltage source inverters (VSIs) with a common dc bus. To address this challenge, this article proposes a minimal ZSCC modulation strategy based on the vector redundancy of paralleled system, which theoretically eliminates the excitation source of ZSCC. Given the redundancy of equivalent vectors, the vectors with zero CMV difference are developed to synthesize the command voltage. Each 60° sector of space vector modulation (SVM) is further segmented into four subsectors. Optimal vector sequences in these subsectors are designed according to the rules of preventing line-to-line voltage reversal and minimizing switching actions, and the implementation of the proposed method is thoroughly investigated, including the determination and duty cycle calculation of subsectors. Compared with the existing works, the proposed method demonstrates superior performance in suppressing ZSCC. The effectiveness of the proposed method is validated on a test platform fed by two paralleled two-level VSIs.