A 25-GS/s 8-bit Current-Steering DAC With ADC-Based Duty-Cycle Detection in 40-nm CMOS

This brief presents a current-steering 25-GS/s 8-bit digital-to-analog converter (DAC) based on a 40-nm CMOS technology. The DAC employs a dual-edge sampling (DES) architecture to reduce the requirement of main clock frequency, optimizing switching noise and improving power efficiency. DES is sensitive to the clock duty cycle. To minimize the image tones and performance degradation caused by duty-cycle errors, a single-slope analog-to-digital converter (ADC)-based duty-cycle detection and correction scheme is proposed, achieving closed-loop background calibration. A T-coil output network is used to extend the bandwidth. The proposed DAC achieves a spurious-free dynamic range (SFDR) of >40 dBc up to the Nyquist frequency and a >12-GHz output bandwidth with sinc roll-off compensation. The active power consumption is about 272 mW under 1.8-/0.9-/−1.8-V power supply.