Optimization of Reading and Writing Performance in Voltage-Gated Spin-Orbit Torque Memory Array

The interplay of spin-orbit torque (SOT) and voltage-controlled magnetic anisotropy (VCMA) exhibits low energy consumption, high speed, and high endurance, promising to achieve high-performance magnetic random access memory (MRAM). In this article, we investigate the reading and writing performance of a voltage-gated SOT (VGSOT) memory array through finite element simulations and micromagnetic simulations. We first analyze the reading mechanism in magnetic tunnel junction (MTJ) arrays. Our analysis shows that simultaneous reading of multiple MTJs leads to a significant reduction in tunnel magnetoresistance (TMR), diminishing the sensitivity of the MTJs and increasing reading power consumption. Two optimization strategies for the reading path are proposed to improve reading accuracy by diminishing the impact of SOT electrode resistance and carefully adjusting the quantity of MTJs. Then, we investigate the writing process with a combination of SOT, VCMA, and exchange bias (EB). Simulation results reveal that applying a gate voltage of 2 V reduces the SOT critical switching current density by 90.45%, significantly improving energy efficiency. By optimizing the timing and pulsewidth of SOT current and VCMA voltage, we demonstrate a reduction of 97.58% in total writing power consumption. These findings offer pivotal insights into optimizing both the reading and writing processes for the practical application of VGSOT-MRAM.