Low Cost TSV Repair Architecture Using Switch-Based Matrix for Highly Clustered Faults

Through-silicon via (TSV), responsible for inter-layer communication in high-bandwidth memory (HBM), plays a critical role in HBM operation. Therefore, faults occur in TSVs can critically impact the entire chips. However, due to their structural characteristics, TSVs are prone to faults occurring both during the manufacturing process and after sale. Accordingly, numerous studies have been conducted on TSV repair methods to ensure TSV reliability. These studies have focused on improving repair rates for the faults occurring within a single TSV repair group. Recent studies have achieved an optimal repair rate by repairing faulty TSVs (FTSVs) up to the number of redundant TSVs (RSTVs) inserted. However, actual faults tend to cluster within TSV repair groups rather than being evenly distributed. In response, this paper proposes a low cost TSV repair architecture (LCTRA) that, while slightly reducing the repair rate for evenly distributed faults, is optimized for repairing highly clustered faults. The proposed method achieves high repair performance for the highly clustered faults with lower area and delay overhead compared to conventional methods, and the repair performance is quantitatively demonstrated through experimental results in various environments.