Efficient Motion Estimation for Video Compression Using Approximate Arithmetic in Sum of Absolute Difference Computation

Designing power-efficient digital systems is essential, particularly for multimedia applications in mobile devices. This paper presents a novel approach to motion estimation in video compression by integrating imprecise Lower-part-OR adders (LOA) into the Sum of Absolute Difference (SAD) computation units. The primary contribution of this work lies in the first application of LOA specifically for motion estimation in High Effi-ciency Video Coding (HEVC). The proposed architecture achieves significant power savings of up to 11.5 %, while maintaining a minimal increase in BjØntegaard Delta Rate (BD- Rate) of just 0.47 % to 0.68 %, showing a negligible impact on video quality. The architecture supports variable block sizes and is scalable for real-time processing of high-definition video, synthesized using 45 nm standard cell technology. This combination of approximate arithmetic with scalable design for video compression represents a unique and practical contribution to the field, offering an optimal balance between power efficiency and video quality preservation.