Design of Approximate Multiplier Using Highly Compressed 5_2 Counter

Approximate computing effectively impacts low-power VLSI circuits by reducing circuit overhead. It introduces minimal error in the output, which does not significantly affect the application. This paper proposes an approximate multiplier constructed using 5_3 and 5_2 counters. The proposed 5_2 counter delivers two outputs instead of three, thereby achieving 60% compression. The overhead of the 5_2 counter circuit is reduced, achieving a power delay product (PDP) improvement of 18%. This reduction comes with an addition of an 6% error rate. The newly designed multiplier has less delay, where the Mean error distance (MED) is kept as low as possible. The complexity of the 5_2 counter is also reduced since the counter uses only a full adder and three gates. This is achieved by applying various error optimization mechanisms. The error parameters, (i) Error Distance (ED), and (ii) Mean Error Distance (MED) are analyzed and compared with existing works. The proposed multipliers are involved in image contrast application with better Peak Signal to Noise Ratio (PSNR) value.