Optimizing the Number of Parallel SiC MOSFET Chips in a Wireless Power Transfer Inverter With Pulse Width Control

In this study, we propose a power device configuration that maximizes the inverter efficiency of a pulse-width-controlled high-power wireless power transfer system. Silicon carbide metal-oxide-semiconductor field-effect transistors are difficult to manufacture in large chips; therefore, they are connected in parallel in high-power circuits. In pulse-width-controlled inverters, inverter losses include conduction and switching losses, which correlate differently with the number of parallel chips. Thus, high efficiency is not achieved simply by increasing the number of parallel chips; the optimal number of parallel chips differs. Considering that the optimal number of parallel chips depends on the pulse width control implementation method (phase shift control and triangular wave comparison), we derive the theoretical equation, employed a circuit simulation to determine the optimal number of parallel chips for each driving method, employed a circuit simulation to confirm the results of the theoretical equation, fabricated a module with the optimal number of parallel chips, and confirmed its effect through experiments. The findings of this study indicate that an asymmetric inverter with varying numbers of parallel chips for four power devices in a full-bridge configuration can maximize efficiency under certain conditions.