Soft-Start Header Power Gating for Inrush Alleviated Current Profile

Inrush current is commonly generated when transitioning from an idle to active state, thus causing power noise and voltage drops. This disrupts core stability, leading to potential errors, increased power delivery challenges, and reduced reliability in high-performance processors. This article presents a novel approach to Power Gating (PG) through a soft-start header that enables a gradual activation, allowing a controlled, stepwise increase in current and thereby alleviating the inrush current effect. In this approach, the width (W) of the header sleep transistor is strategically divided into smaller segments, such as W/2, W/5, W/10, or W/20, where each segment of the sleep transistor is activated sequentially, with fixed delay cells introduced between these segments to introduce a deliberate delay in activation. This staggered approach allows only a fraction of the total transistor width to turn on at any given moment, spreading out the current demand over time. The simulation results for UMC65nm CMOS on Cadence Virtuoso with 20% sleep signal demonstrate a notable reduction (54.55%, 82.01 %, 89.94%, and 93.65% in Plan 1 to Plan 4 respectively) in peak inrush current compared to conventional approaches, underscoring the efficacy of soft-start header PG in power-sensitive applications.