Security Helper Chiplets: A New Paradigm for Secure Hardware Monitoring | IEEE Journals & Magazine | IEEE Xplore

Security Helper Chiplets: A New Paradigm for Secure Hardware Monitoring


Abstract:

Hardware-assisted security features are a powerful tool for safeguarding computing systems against various attacks. However, integrating hardware security features (HWSFs...Show More

Abstract:

Hardware-assisted security features are a powerful tool for safeguarding computing systems against various attacks. However, integrating hardware security features (HWSFs) within complex System-on-Chip (SoC) architectures often leads to scalability issues and/or resource competition, impacting metrics such as area and power, ultimately leading to an undesirable trade-off between security and performance. In this study, we propose re-evaluating HWSF design constraints in light of the recent paradigm shift from integrated SoCs to chiplet-based architectures. Specifically, we explore the possibility of leveraging a centralized and versatile security module based on chiplets called security helper chiplets. We study the cost implications of using such a model by developing a new framework for cost analysis. Our analysis highlights the cost tradeoffs across different design strategies.
Published in: IEEE Computer Architecture Letters ( Volume: 24, Issue: 1, Jan.-June 2025)
Page(s): 61 - 64
Date of Publication: 06 February 2025

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