Vector-Logical In-Memory Simulation of Faults as Truth Table Addresses

A vector-logical mechanism to faults as addresses simulation on smart data structures that eliminate the simulation algorithm of test sets to obtain a testing map for logic functionality is proposed. Smart data structures are represented by a logical vector and its derivatives as truth tables and matrices. The testing map is a matrix whose coordinates are determined by the combinations of all logical faults detected on the binary sets of the exhaustive test. The construction of the testing map is focused on the architecture of in-memory computing based on read-write transactions, which makes the simulation mechanism economical regarding simulation time and energy consumption due to the absence of a central processor. The logic vector, as the only component of the input data, does not require synthesis into a technologically permitted structure of elements. Synthesizing smart data structures based on four matrix operations creates a fault-detected testing map for any logic. The proposed mechanism is focused on servicing SoC IP cores under the IEEE 1500 standard, which can be positively received by engineers in the EDA market. In terms of simplicity and predictability of the size of data structures and the absence of a simulation algorithm of test sets, the proposed mechanism has no analogues in design and industry tests. The introduction presents useful technological trends DAC 61 in the development of computing for the IT industry and academic science of tomorrow. The following areas are highlighted: in-memory computing, immersion computing, and AI computing, which are focused on energy saving and reducing computation time when providing services.