First Demonstration of an N-P Oxide Semiconductor Complementary Gain Cell Memory

This work presents the first experimental demonstration of a Complementary Gain Cell (CGC) memory utilizing an n-type oxide semiconductor transistor (OSFET) as the write transistor and a p-type OSFET as the read transistor. Complementary (n-p) polarities effectively mitigate capacitive coupling of gain cells utilizing voltage sensing. Atomic Layer Deposition (ALD) Indium Tungsten Oxide (IWO) for nFET and Physical Vapor Deposition (PVD) Tin Oxide (SnO) for pFET are utilized. The ALD IWO nFET has a positive $\mathrm{V}_{\text{TH}}$ of $\sim 1.15\mathrm{V}$ and subthreshold slope (SS) of $\sim 80 \ \text{mV}/\text{dec}$. The fabricated SnO pFET has an $\mathrm{I}_{\text{on}}/\mathrm{I}_{\text{off}}$ ratio $> 5\times 10^{4}$. The CGC achieves a measured retention time of 10,000 seconds under a -0.5 V write word line (WWL) standby voltage and can mitigate the WL capacitive coupling issue. The use of both n-type and p-type OS transistors for the 2T gain cell enables the potential for multilayer monolithic 3D integrated memory, paving the way for future “chip city” developments.