Enhancement-Mode Multichannel MoS2 Transistor with Spacer Engineering and Design-Technology Co-Optimization Based on the 8″ Platform

This paper studies highly scaled, multichannel MoS2 transistors (MCTs) through both experiments and simulations. A low-temperature MoS2 synthesis enables a novel integration scheme for MCTs on 8″ wafers with self-aligned source/drain contacts, multiple gate-dielectric-MoS2 channel-dielectric-gate layers stacked on 8″ Si wafers, reduced lithography steps and no sacrificial layers. A 1-channel, double-gate MoS2 transistor features $386\ \mu \mathrm{A}/\mu \mathrm{m}$ on current $(\mathrm{I}_{\text{ON}})$ at $\mathrm{V}_{\text{DS}}=1\ \mathrm{V}$, subthreshold swing SS = 85 mV/dec, and record performance among 2D gate-all-around (GAA) transistors and MCTs. A low drain-induced-barrier-lowering DIBL = 28 mV/V is also demonstrated. We also report the first functional high performance 2-channel MoS2 transistor with $673\ \mu \mathrm{A}/\mu \mathrm{m}\ \mathrm{I}_{\text{ON}}$ and 88 mV/dec SS at 400 nm channel length $(\mathrm{L}_{\text{Ch}})$. In parallel, local-back gate transistors with 1.5 nm physical oxide thickness and 4 nm physical channel length were fabricated to calibrate the device model at extreme scales for design-technology co-optimization (DTCO). Thanks to the DTCO analysis, a projection of multi-channel transistor's scaling, including power, and performance for “1 nm” technology node and beyond is presented.