Power and Thermal Integrity Analysis of High Performance and Low Power CPUs at Sub-2nm Node Designed with Various Advanced Backside PDNs

In this work, we comprehensively evaluated power and thermal integrity of a high performance (HP) CPU and a low power (LP) or high density (HD) CPU in a sub-2nm technology node. Five power delivery networks (PDNs), including conventional front-side PDN, BPR-nTSV, an improved BPR-slit-nTSV, Power-via (PV), and direct backside contact (BSC) BSPDNs, were applied to the HP and HD CPUs, covering all the proposed most advanced backside PDN generic structures up to date. In addition, the combined effect of thermal and power integrity was analyzed by applying the stable CPU working temperature (under 2GHz frequency of 10% data flipping rate conditions) to the IR drop evaluation. Evaluation results show that BSC suffers the highest hotspot temperature among the PDNs, being 14%/2%/1% higher than FSPDN/BPR/PV scenarios respectively due to its extremely thinned wafer. Though the PV BSPDN is of much thinner substrate than the BPR, its hotspot temperature is relatively smaller which results from PV side contact configuration and additional BS metal density. Overall, BSC shows the best power integrity with 91.3%/51.7%/40.6%/10.9% smaller IR drop than FSPDN/BPR+nTSV/BPR+slit-nTSV/PV counterparts at working temperatures, thanks to its highest BS metal connection density and lowest contact resistance. Finally, trade-offs between PDN technology & resource selections and CPU power integrity budget allocation were made by following a Design-Technology-Co-Optimization methodology.