Penta-Level Charge Trap-Based 3D NAND Flash Memory Enabled by Bi-Directional Step-Pulse-Programming and Improvement of Cell Channel Process

We present PLC (Penta-level cell, 5 bits/cell) NAND flash memory using 3D charge-trap-flash (CTF) cell. To achieve PLC cell distribution with proper cell read margin, program noise and short-term data retention (STDR) are addressed as most challenging factors. To make path of charge trap cell for PLC NAND, new program algorithm named as “Bi-directional Step-Pulse-Program (BSPP)” is proposed to manage STDR effect and implemented into our 5^th generation 4D NAND. The BSPP program algorithm improves read window by 67% than the conventional one.