Common-Mode Behavior Optimization for a D-Band Class-AB Power Amplifier Achieving 32 Gb/s in 22-nm CMOS FD-SOI

This article presents a D-band (110–170 GHz) power amplifier (PA) for future 6G wireless infrastructure implemented using the 22-nm CMOS FD-SOI technology from GlobalFoundries. The design features a fully differential power combiner with extremely low insertion loss. The differential nature of the combiner, together with careful local bypass placing and sizing boost the common-mode-rejection-ratio (CMRR) of the output matching network (OMN), improving the power gain and output-referred 1-dB compression point ( $\text {OP1}_{\text {dB}}$ ) of the amplifier. The power stage is biased in deep class AB, inherently increasing back-off efficiency and $\text {OP1}_{\text {dB}}$ , and is cascaded to moderate class AB gain stages for overall flat gain response. Matching networks are implemented using stacked transformers, which are also exploited for supply and bias feed lines. Series resistors are placed on bias lines to stabilize the common-mode (CM) loops and are optimized for linearity. The small-signal gain of the amplifier is 16 dB, and the 3-dB bandwidth (BW) is 21 GHz centered at 140 GHz. The $\text {OP1}_{\text {dB}}$ is 11.4 dBm, and the saturated output power ( ${P}_{\text {sat}}$ ) is 14.6 dBm. The maximum power-added efficiency (PAE) and 6-dB backoff PAE are 10.6% and 2.8%, respectively. Applying a 16-QAM signal without any predistortion, the highest measured baud rate is 8 GB, resulting in a 32-Gb/s data rate, at an average output power and PAE of 8.1 dBm and 4.2%, respectively.