Design and Implementation of Low Power and High-Performance Successive Approximation Analog to Digital Converter

Successive Approximation Register Analog-to-Digital Converters (SAR ADCs) have gainedprominence in low-power applications due to their inherent energy-efficient operation and suitability for integration into modern electronic systems. The quest for further power reduction has led to extensive research in optimizing SAR ADC design. Various techniques have been proposed to address this challenge, ranging from architectural innovations to circuit-level optimizations. Despite being developed SAR ADC benefits more from technological scalability than other ADC designs do precise conversions. The necessity to create ADC designs and circuitry that use the least amount of power while yet fulfilling the performance standards of contemporary electronic systems lies at the heart of the low-power SAR ADC design problem statement. Low-power SAR ADC design specifically aims to minimize power consumption through architectural and circuit-level optimizations, maintain or improve critical performance metrics like resolution, speed, and accuracy, improve system-level energy efficiency, enable integration into energy-constrained electronic systems, and foster innovation in energy efficient implementation. The design is implemented in Cadence Virtuoso system design platform. The design has been implemented with a novel two stage latch comparator design and achieved a low power consumption of 1.254mw.