Enhancing the VTR Flow: Integration of ABC9 via Yosys for Better Technology Mapping and Optimization

This study optimizes the Verilog-to-Routing (VTR) flow, an open-source Computer-Aided Design (CAD) tool. It utilizes ODIN II and Parmys for synthesis, ABC for technology mapping, and Versatile Place and Route for packing, placement, and routing. The ABC9 optimizations, integrated as a pass within the Yosys Open Synthesis Suite, enhance technology mapping and optimization stages and outperform the traditional ABC tool for large, complex designs. These optimizations improve timing behavior in multi-clock designs and include a delay model for Field Programmable Gate Array (FPGA) hard blocks. Various benchmarks assess the effectiveness of the workflow across different design complexities and FPGA architectures, including the utilization of hard blocks.