Design and Comparison of 4x4 Bit Multipliers Utilizing CMOS 45nm and FinFET Technology

This paper presents a performance analysis of two 4x4 binary multipliers implemented using different architectures: an array multiplier based on carry-save adders and a ripple carry multiplier using ripple carry adders. The multipliers were simulated using Cadence in 45nm CMOS and 18nm FinFET technologies. Key metrics such as power dissipation and delay time were evaluated for each multiplier. The power dissipation of the 4x4 array multiplier is higher than that of the ripple carry multiplier by 1.3 times in CMOS 45nm, and 1.52 times in FinFET.