A Fully-Customized RTL to GDS Design and Verification of Low-Power Cache Memory

In this paper, we have reported low-power cache memory with DFT and scan chain techniques utilizing RTL to GDS (Register-Transfer Level to Graphic Design System) implementation in the Cadence Innovus tool using 45 nm technology. In the frontend design, the gate level synthesis is carried out using the Cadence Genus tool with input files i.e., the Verilog file, design constraint, and library file which also generates the gate level netlist file. In the backend design, the physical design implementation is proposed including different intermediate levels such as synthesis, placement, routing, and timing analysis to optimize the design in terms of power, timing, and area. We have proposed a low-power cache memory including a clock gating technique to reduce the dynamic power consumption. It is estimated that the total power consumption of the proposed Low Power Cache Memory design is 20% less than the standard cache memory design. We have studied the superflow, a fully customized RTL to GDS design flow tailored for low-power cache memory, and also reported power and timing analysis. This paper emphasizes the importance of each stage in the ASIC design cycle, highlighting every phase-starting from design specification, architecture design, RTL coding, synthesis, place and route, and verification-plays a critical role in shaping the final performance with ample opportunities for future research optimizing the design for enhanced performance.