Novel Sign-Magnitude Binary to Balanced-Ternary Encoder on Basys3 Artix7 FPGA

In the realm of digital systems, binary representation has been the predominant method for data encoding and processing. However, alternative numbering systems such as ternary (base-3) have gained considerable attention over binary due to its ability to reduce interconnect complexity for identical data processing. Balanced ternary offer several advantages over unbalanced ternary in certain applications. This report outlines novel binary to balanced ternary encoder that accepts 9-bit sign-magnitude binary data (-255 to +255) and generates 6-trit ternary equivalent in BET (Binary Encoded Ternary) format. The theoretical analysis is explained and the corresponding verilog code is simulated using Xilinx-vivado software to validate the idea. After behavioral simulation, the circuit is synthesized and implemented for the target device Xilinx Basys3 Artix-7 FPGA: XC7 A35T -1 CPG236C. Post implementation bit stream is downloaded on to the target FPGA for prototype verification.