Design and Implementation of CML Frequency Divider Circuit Using 90nm Technology

The objective of this paper is to design a current mode logic (CML) frequency divider in CMOS 90nm technology. The fundamental idea behind this paper is to understand the basic operation of CML circuit using a $T$ flip-flop-based frequency divider. Combining Current Mode Logic (CML) with $T$ flip-flops creates a powerful solution for building high-speed frequency dividers. This introduces a frequency divider circuit that takes advantage of CML technology and the unique properties of $T$ flip-flops to split frequencies efficiently. $T$ flip-flops work by toggling their state with every clock pulse, effectively cutting the input frequency in half with each flip-flop stage. A frequency divider is needed in the PLL loop to allow the use of a low-frequency reference clock that is typically provided by a highly accurate off-chip crystal oscillator. Using CML in this design boosts the circuit's performance, making it faster and more energy-efficient than traditional logic circuits. CML's current steering and differential signaling help to achieve higher speeds and better handle noise, less power, less area, and low voltage making it ideal for demanding digital applications. This abstract covers how the CML -based frequency divider works, and its benefits for high-speed tasks.