Modeling and Verification of Processing Engines in SAR Imaging SoC

With the development of real-time requirements for Synthetic Aperture Radar (SAR) imaging technology, SAR imaging processing SoC (System on Chip) has become an important research field at present. The subsystem for SAR imaging processing in the SAR imaging SoC needs to be fully verified during the development process. This article designs a UVM-based random verification environment, focusing on the verification requirements of key computing engines and interaction engines in the SAR imaging processing SoC. At the same time, a modeling method for computing engines and interaction engines is proposed, which can quickly and accurately describe the functions and behaviors of processing engines. Collaborating with the verification environment and the reference C model, the design under test achieves satisfactory coverage results. Consequently, the functionality of the processing engines within the subsystem can be comprehensively and effectively verified. The content studied in this article has certain value for the engineering verification implementation of SAR imaging algorithms in the SoC.