A Parallel Mechanism for Fast Digital SIC in Full-Duplex ISAC systems

A novel parallel mechanism for rapid digital-domain self-interference cancellation (SIC) in full-duplex (FD) integrated sensing and communication (ISAC) systems is proposed. The processing delay is minimized by employing a parallel cancellation architecture and substituting filtered sampling symbols with known modulation symbols, thus enabling effective and timely SIC for radar sensing. The proposed parallel SIC technique is presented through comprehensive system modeling, algorithm definition, feasibility assessment, numerical simulations, and experimental validations. The analysis shows that the proposed algorithm, with its high convergence speed, can effectively eliminate self-interference under severe conditions of self-interference and high-frequency variations, thereby enhancing the SIC capabilities of the full-duplex ISAC platform and contributing to the improvement of sensing performance.