Impact of Analog Bandwidth and Sampling Clock Jitter on Performance of ADC Bandwidth Doubler with Image-Rejection Downconversion and Oversampling

In this paper, we evaluate the signal transmission performance of an analog-to-digital converter (ADC) bandwidth doubler with image rejection and oversampling via computer simulation, where the analog bandwidth of the ADC and the jitter of the sampling clock are included. A comparison between the proposed bandwidth doubler and the ADC without bandwidth division using the PAM4 signal shows improved performance using the bandwidth doubler than without bandwidth division.