A 200 GHz Area-Efficient 4-stage Power Amplifier with Stacked Output Stage in 22 nm FDSOI

This paper presents a compact, low DC-power four-stage G-Band power amplifier (PA) integrated into a 22 nm fully-depleted silicon-on-insulator (FDSOI) technology. The three common-source driver stages and the output stage utilize the capacitive neutralization technique for gain-boosting. The output stage is implemented as a tuned stacked-FET amplifier for further gain and output power enhancement. Low-loss stacked transformers are employed as matching networks to achieve a small core-area footprint of 0.024 mm². The PA attains a gain of 12.5 dB, a 1 dB output compression point OP1dB of -4 dBm, and an extrapolated saturated output power $\mathbf{P}_{\mathbf{sat}}$ of 3.7 dB at 200 GHz, based on simulation and measurement. Supplied by 1.6 and 0.85 V, the circuit's DC-power consumption is below 57 m W.