A D-Band CMOS Power Combiner With Low Insertion Loss

A D-band low-loss power combiner is proposed by using 65-nm CMOS technology. The power combiner is composed of distributed transmission lines, a common transmission line, shunt capacitors, and an isolation resistor. By integrating an RF pad network modeled as a transmission line and a load capacitor, the proposed power combiner has both compact size and low loss. It is also designed to have a lower characteristic impedance at the same transmission line length as the conventional capacitively loaded Wilkinson power combiner. The proposed power combiner is implemented at a transmission line characteristic impedance of 55 Ω and a total transmission line length of 71.8° on a core size of 0.16 × 0.15 mm² including an RF pad. The measurement results of the proposed power combiner show minimum insertion losses of 0.7 dB and bandwidth of 112−182 GHz. The simulated isolation between input ports is 20 dB or better in the 135 to 168 GHz frequency range.