A 37-43 GHz Step Attenuator with High Linearity and Low Phase Variation in 65-nm CMOS

This paper presents a 37-43 GHz step attenuator designed for high linearity, low phase variation, and minimal input/output return loss. To mitigate the relatively large area issues of the conventional digital step attenuators, a modified differential bridge-T-type structure is proposed. A phase compensation technique utilizing tail capacitors and shunt inductors is incorporated to achieve minimal phase variation. Fabricated in a 65-nm CMOS process, the proposed attenuator achieves a maximum attenuation of 3 dB with a precise 1-dB step. Across the entire operating bandwidth, the achieved rootmean-square (RMS) amplitude error is lower than 0.16 dB with a minimum RMS phase error of less than 1.5°. Besides, the attenuator input and output return loss is below 11.6 dB over 37-43 GHz with 6.6 - 7.6 dB insertion loss. Excluding the pads, the attenuator core chip area is 0.081 mm².