A FPGA-Based Accelerator Design for Speaker Verification using 1D-CNN

The one-dimensional convolutional neural network (1D-CNN) has been widely used in large-scale speaker voice verification due to its effectiveness. The primary objective of this study is to construct a 1D-CNN model for speaker verification and to design a hardware accelerator on a low-cost hardware platform. We thoroughly analyzed the impact of different parallel parameters on the computational process and proposed a parallelism search method to determine optimal architectural design parameters. Experiments of the proposed 1D-CNN on the FPGA ZYNQ XCZU2CG demonstrated that our 1D-CNN accelerator architecture achieves an overall throughput of 63.67 GOPS at 200MHz with power consumption of only 2.13W, and a DSP efficiency of 0.354 GOP/s/DSP.