Enhancing DFT Performance: The Power of Scan Compression and Lockup Latches

With the miniaturization of transistors and the exponential growth in transistor count within integrated circuits, the challenges of controlling and observing internal nodes have become increasingly pronounced, particularly in sequential circuits. This has led to the complexities associated with fault localization and debugging. Design for Testability (DFT) offers a valuable solution by enabling efficient fault detection within the circuit under test, reducing simulation time and minimizing area overhead. Various DFT techniques have been proposed for pattern simulation, and this paper focuses on comparing two prominent approaches: scan compression and internal scan. The paper discusses the inclusion of lockup latches, which enhance performance by improving test coverage, reducing test data volume, and minimizing test time. Experiments conducted on a range of benchmark circuits demonstrate that both scan compression and lockup latch significantly reduce simulation time, and test data volume while achieving high fault coverage, with a modest increase in area overhead.