Front-End Readout ASIC Design for Neutron Detectors

The traditional detector readout electronics take up a large amount of space and consume high power, limiting the system's integration level and not meeting the requirements of new types of detectors. To meet the demand for high-efficiency, high-resolution neutron detectors, an ASIC chip based on GF 0.13μm CMOS technology has been designed. This chip adopts a mixed-signal design and integrates 32 channels on a single chip. It mainly includes a charge-sensitive amplifier (CSA), shaping-filter circuit (CR-RC), calibration signal configuration circuit, and decoder circuit. Test results show that the chip has low power consumption, relatively good channel consistency, excellent linearity in the range of 0-100fC, and a maximum counting rate of up to 2MHz.