Design And Performance Analysis of Different Low-Power Multiply-Accumulate (MAC) Units

The design of low-power Multiplier Accumulator (MAC) units has become crucial for energy-efficient computing systems. MAC units play a vital role in various applications such as digital signal processing (DSP), multimedia processing, image processing, and neural networks, where efficient multiplication and accumulation operations are required. This paper presents an overview of the key considerations and strategies involved in designing a low-power MAC unit to achieve optimal power consumption while maintaining performance. The design process starts with the selection of different energy-efficient multipliers and adder components. Power-efficient multiplier architectures such as the Carry save multiplier, Vedic multiplier, and Wallace tree multiplier are employed to minimize power consumption during multiplication operations. Similarly, low-power adders including carry-select adders, carry-skip adders, carry-save adders, and carry-lookahead adders are utilized to reduce power dissipation during addition and a low-power accumulator is designed for accumulation operations. The design of MAC units involves a trade-off between speed (propagation delay) and efficiency (power consumption) This paper compares designed MAC unit modules based on these factors. The design schematics and simulations of low-power MAC units are done using adequate libraries, with the mentor graphics Tanner EDA suit’s S-edit, T-Spice, and W-edit software using 45nm CMOS technology model files.