High Speed Data Transfer from External Interface to Memory using FIFO and AXI DMA

In this era of fast-growing electronics and data intensive applications, the need for achieving an efficient and high-speed data transfer between external application and memory has become paramount. The need for a high-speed data transfer system which can transfer data seamlessly has increased. This project focuses on developing a high-speed data transfer system that can help in fast and efficient data transfer between an external device and a memory (DRAM) using an AXI (Advanced eXtensible Interface) DMA.The core components of our project include a Sample Generator, which is seamlessly integrated with an AXI4 Stream FIFO, an AXI DMA, and the Zynq Processing System that provides access to the DRAM. Sample generator provides data samples, AXI4 Stream FIFO acts as the buffer, DMA supervises the data transfer and Zynq processing provide access to the DRAM. This project focuses on the of AXI DMA in facilitating direct memory access, streamlining data movement, and enhancing overall system performance. A block integration of all the necessary IP blocks its verification and bitstream generation will be done in Xilinx Vivado software. Beyond the hardware design, the software aspect involves the creation of an application project in Xilinx SDK software to interact with the custom block design. The main aim of this project is to move 8192 words of data from sample generator to DRAM through the AXI4 Stream Data FIFO, AXI DMA and the Zynq processing system. The resource utilization, power usage and timing analysis will be calculated for different FIFO parameters (100MHz-100MHz, 100MHz-50MHz, 200MHz-100MHz)