SiC Power Module Design using Flip Chip Configuration to Reduce Common-Mode Noise

Silicon carbide (SiC) semiconductors have higher switching speeds compared to their Silicon counterparts, which increases common mode (CM) noise. This study proposes a new configuration of power module which utilizes flip chip and copper lead bonding techniques to reduce CM capacitance. The low side bare dies are flipped, allowing the pulsating terminal to be placed above the direct bonded copper (DBC) as a copper lead. The prototype module was able to achieve a 90% reduction in CM capacitance. A double pulse test proved a 77% reduction in peak CM current during turn off and a 40% reduction during turn on. Thermal cycling tests confirmed the reliability of the gate pad connection of the flipped chips.