An efficient technique to improve NORA CMOS testing

This paper presents a novel circuit technique to improve the testability of NORA (NO RAce) CMOS circuits. It is based on the structure, properties and operations of NORA CMOS. The precharge and evaluation properties of NORA CMOS enable one to design simple testing circuit for output stuck-at-zero, stuck-at-one, stuck-open and stuck-on faults. Area and time considerations, as well as the applications of this testability enhancement technique are also discussed.