Design techniques for switched-capacitor adaptive line equalizer

This paper describes design techniques for a switched capacitor adaptive line equalizer which is applied to high speed (200 kb/s) digital transmission over analog subscriber loops. An equalizer transfer function is approximated so as to minimize intersymbol interference of an isolated pulse response. Optimum pole-zero location, which is suited to line characteristics in a wide frequency band, is also discussed. In order to attain high accuracy capacitor ratios using a small unit capacitor, capacitor values are rounded off into equivalent integer values, and are discretely optimized using pole-zero deviation as an error criterion. The equalizer has a finite number of frequency responses which correspond to line lengths. Gain and delay time differences between the adjoining step responses are compressed. The designed switched capacitor line equalizer was fabricated using 3-
\mu
m CMOS technology. Measured data were very close to designed performances.