A 1.62 – 10-Gb/s CDR Using Wide-Range VCO With Linearized KVCO

A clock and data recovery (CDR) with a voltage-controlled oscillator (VCO) calibration circuit is proposed for supporting transmission speeds from 1.62 Gbps to 10 Gbps. It has a dual-loop structure for frequency and phase locking while using a VCO based on a ring oscillator to support a wide operating range. The VCO calibration circuitry ensures that the VCO’s gain, kVCO, is set within a consistent range over a wide data rate by adaptively setting the operating frequency range of the VCO based on the frequency of the incoming training pattern. The proposed CDR is implemented by using a 40-nm CMOS process with a voltage supply of 1.2 V. It occupies the area of 0.08mm2 while having power efficiency of 2.5 pJ/bit. The proposed CDR improved the peak-to-peak time jitter of the recovered clock from 51.1ps to 31.25ps at the data rate of 8.1 Gbps by using the VCO calibration circuit. The proposed VCO calibration for the CDR also reduced the distribution of the peak-to-peak time jitter of the recovered clocks between the evaluated chips by 44%.